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rev. 1.10 1 november 24, 2011 rev. 1.00 pb november 25, 2011 HT82V46 16-bit, 45msps, 3-channel ccd/cis analog signal processor features ? operating voltage: 3.3v ? guaranteed wont miss codes ? 9-bit programmable gain ? correlated double sampling ? 8-bit programmable offset ? programmable clamp voltage ? 8-bit wide multiplexed data output format ? 8-bit only output mode ? 4-bit multiplexed nibble mode ? internal voltage reference ? programmable 4-wire serial interface ? maximum conversation rate up to 45 msps ? 28-pin ssop package applications ? flatbed document scanners ? film scanners ? digital color copiers ? multifunction peripherals general description the HT82V46 is a complete analog signal processor for ccd imaging applications. it features a 3-channel architecture designed to sample and condition the outputs of tri-linear color ccd arrays. each channel consists of an input clamp, correlated double sampler (cds), offset dac and programmable gain amplifier (pga), and a high performance 16-bit a/ d converter. the cds amplifers may be disabled for use with sensors such as contact image sensors (cis) and cmos active pixel sensors, which do not require cds. the 16-bit digital output is available in 8-bit wide multiplexed format. the internal registers are programmed through a 4-wire serial interface, which provides gain, offset and operating mode adjustments. the HT82V46 operates from a single 3.3v power supply, typically consumes 528mw of power. block diagram sck refb reft dvss avss avss adck cds 2 cds 1 16 - bit adc 16 : 8 : 4 mux 16 8 sen sdi od [ 0 : 6 ] oeb vinr avdd cml dvdd ving vinb vrlc / vbias dvdd od [ 7 ]/ sdo cds bandgap reference rlc rlc rlc timing control c 1 s c 2 s clp cds cds 3 : 1 mux 8 9 4 9 4 pga pga pga + + + dac offset dac offset dac offset rlc dac serial control interface pga reg offset reg setup reg 1 ~ reg 6 green blue red green blue red + + + 2 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 2 november 24, 2011 HT82V46 pin assignment

pin description pin name i/o description vinr ai analog input, red channel a vss p analog ground dvdd p digital driver power oeb di output enable, active low cds2 di cds video level sampling clock cds1 di cds reference level sampling clock adck di adc sampling clock d vss p digital driver ground sen di serial interface enable , active h i gh dvdd p digital driver power sdi di serial d ata i nput for serial control interface sck di clock input for serial control interface od0~od6 do digital data output od7/sdo do when register bit oeb= 0, opd= 0 and sen has been pulsed high, this pin use as serial d ata out put for serial control interface . otherwise, this pin use as digital data output. avdd p analog supply a vss p analog ground ref b ao adc bottom reference voltage decoupling ref t ao adc to p reference voltage decoupling cml ao internal bias level decoupling vrlc/vbias aio selectable analog output voltage for rlc or single-ended bias reference. this pin would typically be connected to agnd via a decoupling capacitor. vrlc can be externally driven if programmed hi- z . ving ai analog input, green channel vinb ai analog input , blue channel type: ai= analog input; ao= analog output; aio=analog in/out, di= digital input; do= digital output; p= power. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 3 november 24, 2011 HT82V46 absolute maximum ratings supply voltage ......................................................................................................................... v ss -0.3v to v ss +4.3v input voltage ........................................................................................................................... v ss -0.3v to v dd +0.3v storage temperature ........................................................................................................................... -50c to 125c operating temperature ............................................................................................................................. 0c to 70c analogue supply power .......................................................................................................................... 3.0v to 3.6v digital supply power ............................................................................................................................... 3.0v to 3.6v note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics symbol parameter test conditions min. typ. max. unit power supply av dd analogue supply power D 3.0 3.3 3.6 v dv dd digital supply power D 3.0 3.3 3.6 v digital inputs v ih high level input voltage D 0.7*dv dd D D v v il low level input voltage D D D 0.2*dv dd v i ih high level input current D D D 1 a i il low level input current D D D 1 a c i input capacitance D D 5 D pf digital outputs v oh high level output voltage i oh = 1ma dv dd -0.5 D D v v ol low level output voltage i ol = 1ma D D 0.5 v i oz high impedance output current D D D 1 a digital i/o pins v ih applied high level input voltage D 0.7*dv dd D D v v il applied low level input voltage D D D 0.2*dv dd v v oh high level output voltage i oh =1ma dv dd -0.5 D D v v ol low level output voltage i ol =1ma D D 0.5 v i il low level input current D D D 1 a i ih high level input current D D D 1 a i oz high impedance output current D D D 1 a www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 4 november 24, 2011 HT82V46 a.c. characteristics av dd= dv dd =3.3v, av ss= dv ss =0v, ta=25c, 3-channel mode, adck=45mhz unless otherwise stated. symbol parameter test conditions min. typ. max. unit overall system specifcation (including 16-bit adc, pga, offset and cds functions) maximum conversion rate D D 45 D msps full-scale input voltage range (see note 1) lowref= 0, g max =7.5 typ. D 0.25 D v p-p lowref= 0, g min =0.65 typ. 3.03 v p-p full-scale input voltage range (see note 1) lowref= 0, g max =7.5 typ. D 0.15 D v p-p lowref= 0, g min =0.65 typ. 1.82 v p-p v in input signal limits (see note 2) D av ss -0.3 D av dd +0.3 v full-scale transition error gain=0db; pga[8:0]=1a(hex) D 30 D mv zero-scale transition error gain=0db; pga[8:0]=1a(hex) D 30 D mv dnl differential non-linearity D D 2 D lsb inl integral non-linearity D D 50 D lsb channel to channel gain matching D D 1.5 D % total output noise min gain D 30 D lsb rms max gain 300 lsb rms references v rt upper reference voltage lowref=0 1.95 2.05 2.25 v lowref=1 1.85 v v rb lower reference voltage lowref=0 0.95 1.05 1.25 v lowref=1 1.25 v cml input return bias voltage D D 1.5 D v v rtb diff. reference voltage (v rt - v rb ) lowref=0 0.90 1.0 1.10 v lowref=1 0.6 v rlc dac (reset-level clamp d/a converter) resolution D D 4 D bits v cstep step size cdacrng=0 D 0.173 D v/step cdacrng=1 0.110 v/step v cbot output voltage at code 0h cdacrng=0 D 0.4 D v cdacrng=1 0.4 v v ctop output voltage at code fh cdacrng=0 D 3.00 D v cdacrng=1 2.05 v dnl differential non-linearity D -0.5 D +0.5 lsb inl integral non-linearity D D +/-1 D lsb offset dac resolution D D 8 D bits step size D D 2.04 D mv/step output voltage code 00(hex) D -260 D mv code ff(hex) +260 mv www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 5 november 24, 2011 HT82V46 symbol parameter test conditions min. typ. max. unit programmable gain amplifer resolution D D 9 D bits gain equation D 0.66 + pga[8:0] * 7.34 / 511 v/v g max max gain, each channel D D 7.5 D v/v g min min gain, each channel D D 0.65 D v/v channel matching D D 1 5 % a/d converter resolution D D 16 D bits speed D D 45 D msps full-scale input range 2*(v rt - v rb ) lowref=0 D 2.0 D v lowref=1 1.2 v supply currents total supply current D D 160 D ma analogue supply current D D 130 D ma digital supply current D D 30 D ma power down mode D D 130 D a ote: 1. full-scale input voltage denotes the pea input signal amplitude that can be gained to match the adc full- scale input range. 2. input signal limits are the limits within which the full-scale input voltage signal must lie. timing specifcation av dd =dv dd =3.3v, av ss =dv ss =0v, ta=25c, adck=45mhz unless otherwise stated. symbol parameter test conditions min. typ. max. unit clock parameter t adc adck period D 22 D D ns t adh adck high period D 10 11 D ns t adl adck low period D 10 11 D ns t c1 cds1 pulse high D 5 D D ns t c2 cds2 pulse high D 5 D D ns t c1fc2r cds1 falling to cds2 rising D 0 D D ns t adfc2r adck falling to cds2 rising D 4 D D ns t adrc2r adck rising to cds2 rising D 2.5 D D ns t adfc2f adck falling to cds2 falling D 4 D D ns t c2fadr cds2 falling to adck rising 2 D 1 D D ns t adfc1r 1 st adck falling after cds2 falling to cds1 rising D 1 D D ns t pr3 3-channel mode pixel rate D 66 D D ns t pr2 2-channel mode pixel rate D 44 D D ns t pr1 1-channel mode pixel rate D 22 D D ns t od output propagation delay D D 8 12 ns lat output latency. from 1 st adck rising edge after cds2 falling to data output D D 7 D adck periods www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 6 november 24, 2011 HT82V46 symbol parameter test conditions min. typ. max. unit serial control interface t sck sck period D 83.3 D D ns t sckh sck high D 37.5 D D ns t sckl sck low D 37.5 D D ns t sdis sdi set-up time D 6 D D ns t sdih sdi hold time D 6 D D ns t ckfenr sck falling to sen rising D 12 D D ns t enfckr sen falling to sck rising D 12 D D ns t sen sen pulse width D 60 D D ns t enfsd7 sen falling to od7/sdo output the d7 of register data D D D 30 ns t ckfsd6 sck falling to od7/sdo output the d6 of register data D D D 30 ns t ckfod7 sck falling to od7/sdo output od7 D D D 30 ns 1rwh dddddrd d r d sd r d r r . rsdsrd function description introduction 7kh 7 fdq dpsoh xs r kuhh lqsx qdpho 5 dqg lpxodqhrxo 7kh ghylfh khq surfhh kh dpsohg ylghr lqdo zlk uhshf r kh ylghr uhh ohyho ru dq lqhuqdoohhuqdoo hqhudhg uhihuhqfh ohyho iru lqdo surfhlq dfk surfhlq fkdqqho frql ri dq qsx dpsolq eorfn zlk rslrqdo 5hh /hyho odpslq 5/ dqg ruuhodhg rxeoh dpsolq dq el surudppdeoh riih dqg d el 3urudppdeoh dlq psolhu 3 7kh khq frqyhu hdfk uhxolq dqdorxh lqdo r d el glldo zrug 7kh glldo rxsx iurp kh l suhhqhg rq dq el zlgh ex 2qfkls frquro uhlhu ghhuplqh kh frqxudlrq ri kh ghylfh lqfoxglq kh riih dqg dlq dssolhg rq hdfk fkdqqho 7khh uhlhu duh surudppdeohylddhuldolqhuidfh internal power-on-reset (por) circuit internal por circuit is powered by av dd d d r r d d d d sr s d r typ. r dd d d d typ. r dd r typ. r dd dd sr r dd dd r dd d r typ. d dd r r r rr d d d d r d r d r r rd r sr power management 7kh ghylfh ghidxo l ixoo hqdeohg 7kh 5hlhu l doorz kh ghylfh r eh ixoo srzhuhg grzq zkhq h orz qglylgxdo eorfn fdq eh srzhuhg grzq xlq kh el lq hxs 5hlhu :khq lq ru prgh kh xqxhg lqsx fkdqqho duh dxrpdlfdoo gldeohgruhgxfhsrzhufrqxpslrq references the adc reference voltages are derived from an internal bandgap reference, and buffered to pins reft and refb, where they must be decoupled to ground. pin cml is driven by a similar buffer, and also requires decoupling. the output buffer from the rlcdac also requires decoupling at pin vrlc/ vbias. cds/non-cds processing for ccd type input signals, containing a fixed reference level, the signal may be processed using correlated double sampling (cds), which will remove pixel-by-pixel common mode noise. with cds processing the input waveform is sampled at two different points in time for each pixel, once during the reference level and once during the video level. to sample using cds, register bit cds must be set to 1 (default). this causes the signal reference to come from the video reference level as shown in figure 1. the video sample is always taken on the falling edge of the input cds2 signal (c2 s r ds r d www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 7 november 24, 2011 HT82V46 edge of the cds1 input signal (c1 s ). for input signals that do not contain a reference level (e.g. cis sensor signals), non-cds processing is used (cds=0). in this case, the video level is processed with respect to the voltage on pin vrlc/vbias. the vrlc/vbias voltage is sampled at the same time as cds2 samples the video level in this mode. in ws mode the input video signal is always sampled on the 1st rising edge of adck after cds2 has gone low (video sample) regardless of the operating mode. if in non-cds mode (cds=0) the voltage on the vrlc/vbias pin is also sampled at this point. in cds-mode (cds=1) the position of the reference sample (c1 s ) can be varied, under control of the cdsref[1:0] register bits, as shown in figure11. line-by-line operation certain linear sensors give colour output on a line- by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. often the sensor will have only a single output onto which these outputs are time multiplexed. the HT82V46 can accommodate this type of input by setting the lnbyln register bit high. when in this mode the green and blue input pgas are disabled to save power. the analogue input signal should be connected to the vinr pin. the offset and gain values that are applied to the red input channel can be selected, by internal multiplexers, to come from the red, green or blue offset and gain registers. this allows the gain and offset values for each of the input colours to be setup individually at the start of a scan. when register bit acyc=0 the gain and offset multiplexers are controlled via the intm[1:0] register bits. when intm=00 the red offset and gain control registers are used to control the red input channel, intm=01 selects the green offset and gain registers and intm=10 selects the blue offset and gain registers to control the red input channel. when register bit acyc=1, auto-cycling is enabled, and the input channel switches to the next offset and gain registers in the sequence when a pulse is applied to the cds1 input pin. the sequence is red green blue red offset and gain registers applied to the single input channel. a write to the auto-cycle reset register (address 05h) will reset the sequence to a known state (red registers selected). when auto- cycling is enabled, the cds1 pin cannot be used to control reset level clamping. the clpctl bit may be used instead (enabled when high, disabled when low). when auto-cycling is enabled, the cds1 pin cannot be used for reference sampling (i.e. cds must be set to 0). c 2 s clp 4 4 rlc dac c in cdacpd cdac [ 3 : 0 ] cds = 1 = 0 c 1 s ( cds = 1 ) or c 2 s ( cds = 0 ) video sample capacitor reference sample capacitor vrlc / vbias vinr figure 1 cds/non-cds input confguration www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 8 november 24, 2011 HT82V46 adck: 45mhz; cds: available adck:cds2 max. sample rate (msps) register bit r/g/b of pga mode 1ch 2ch ch[1:0] red green blue 3:1 15 0 0 xx v 1 v 1 v 1 3-channel 2:1 22.5 0 1 xx v 1 v 1 x 1 2-channel 1:1 45 1 0 00 v 1 x 1 x 1 1-channel 01 x 1 v 1 x 1 10 x 1 x 1 v 1 1 0 11 invalid 1 1 xx invalid where x 1 : disable; v 1 : enable table 1 nm operating modes t c 1 t c 2 t adfc 1 r t adh t adl hb : high byte ; lb : low byte n - 2 n - 4 cds 1 cds 2 adck analog input ( r , g , b ) od [ 7 : 0 ] pixel n t od t od pixel n + 1 pixel n + 2 t pr 3 t c 2 fadr t adfc 2 r t c 1 fc 2 r r hb lb r g hb lb g b hb lb b r hb lb r g hb lb g b hb lb b r hb lb r g hb lb g b hb lb b hb r b hb lb b n - 1 n - 3 t adc figure 2 3-channel cds analog input timing analog input signal sampling there are nm and ws two operating modes of HT82V46. it can be selected by register bit ws. nm mode (ws=0; normal mode) the adck speed can be specified along with the adck:cds2 ratio to achieve the desired sample rate as table 1. nm mode timing diagram see figure 2 , figure 3 and figure 4. ws mode (ws=1) it requires double rate adck and pixel rate cds2 input. cds1 pin performs same function as rlc/ acyc pin. a programmable detect circuit allows the sampling point derived from cds2 pin. when set c2det to 1, the circuit detects either a rising or falling edge (determined by c2pos control bit) on the cds2 input pin and generates an internal intc2 pulse. when c2pos=1, a positive edge transition is detected and when c2pos=0, a falling edge transition is detected. intc2 can optionally be delayed by a number of adck periods, specified by the c2dly[2:0] bits. figure 5 shows the sampling point occurs on the frst rising adck edge after this internal cds2 pulse. ws mode timing diagram see figure 6 , figure 7, figure 8 and figure 9. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 9 november 24, 2011 HT82V46 t c 2 t t adfc 2 r t c 2 fadr c 1 fc 2 r t adfc 1 r t adh t adl hb : high byte ; lb : low byte n - 4 n - 5 cds 1 cds 2 adck analog input ( r , g ) od [ 7 : 0 ] pixel n t od t od pixel n + 1 pixel n + 2 pixel n + 3 t pr 2 r hb r lb g hb g lb hb r lb g hb g lb r hb r lb g hb g lb r hb g hb g lb r n - 3 n - 2 n - 1 t c 1 figure 3 2-channel cds analog input timing t c 2 t t c 2 fadr c 1 fc 2 r t adfc 1 r hb : high byte ; lb : low byte n - 8 cds 1 cds 2 adck analog input ( r ) od [ 7 : 0 ] pixel n t od t od pixel n + 1 pixel n + 2 pixel n + 3 t pr 1 n - 7 n - 6 r hb r lb r hb r lb r hb r lb r hb r lb n - 5 adfc 2 r t c 1 t adfc 2 f t adh t adl t adc figure 4 1-channel cds analog input timing note: 1. the relationship between input video and sampling is controlled by cds2 and cds1. 2. when cds2 is high the input video signal is connected to the video level sampling capacitors. 3. when cds1 is high the analog input video signal is connected to the reference level sampling capacitors. 4. cds1 must not go high before the frst falling edge of adck after cds2 goes low. 5. it is required that the falling edge of cds2 should occur before the rising edge of adck. 6. in 1-channel cds mode it is not possible to have a equally spaced video and reference sample points with a 45mhz adck. 7. non-cds operation is also possible; cds1 is not required in this mode. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 10 november 24, 2011 HT82V46 intc 2 cds 2 adck c 2 dly [ 2 : 0 ] = 000 c 2 pos = 1 c 2 dly [ 2 : 0 ] = 001 c 2 dly [ 2 : 0 ] = 111 intc 2 c 2 dly [ 2 : 0 ] = 000 c 2 pos = 0 c 2 dly [ 2 : 0 ] = 001 c 2 dly [ 2 : 0 ] = 111 c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s c 2 s figure 5 internal cds2 pulses generated by programmable cds2 detect circuit adck : 45mhz mode timing req. adck:cds2 sample rate (msps) register bit cdsref[1:0] ws mode4 2ch 1ch cds en mode1: 3-ch pixel-by-pixel 2n:1, n 3 7.5 D 1 0 0 0 1 1 0 mode2: 1-ch line-by-line 2n:1, n 3 7.5 D 0 1 1 0 mode3: 1-ch line-by-line 3:1 22.5 00 0 0 1 0 mode4: 1-ch line-by-line 2:1 22.5 D 1 0 0 0 table 2 ws operating modes note: 1. in 1-channel mode, setup register 3 bits 7:6 ch[1:0] determine which input is to be sampled. 2. for colour line-by-line, set register bit lnbln. for input selection, refer to table 1, colour selection description in line-by-line mode. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 11 november 24, 2011 HT82V46 analog input ( r , g , b ) cds 2 adck od [ 7 : 0 ] dly [ 1 : 0 ] = 00 hb : high byte ; lb : low byte r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb b lb b lb 16. 5 adck r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb b lb r hb r lb g hb g lb b hb b lb dly [ 1 : 0 ] = 01 dly [ 1 : 0 ] = 10 dly [ 1 : 0 ] = 11 figure 6 mode1 : 3-channel pixel-by-pixel analog input ( r , g , b ) cds 2 adck od [ 7 : 0 ] dly [ 1 : 0 ] = 00 hb : high byte ; lb : low byte ; x : invalid data hb lb hb lb 16 . 5 adck hb lb hb lb hb lb dly [ 1 : 0 ] = 01 dly [ 1 : 0 ] = 10 dly [ 1 : 0 ] = 11 x x x x x x x x x x x x x x x x x x x x x x x x hb lb hb lb hb lb hb lb figure 7 mode2 : 1-channel line-by-line www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 12 november 24, 2011 HT82V46 analog input ( r , g , b ) cds 2 adck od [ 7 : 0 ] dly [ 1 : 0 ] = 00 23 . 5 adck hb : high byte ; lb : low byte hb lb dly [ 1 : 0 ] = 01 dly [ 1 : 0 ] = 10 dly [ 1 : 0 ] = 11 hb lb hb lb hb lb hb lb hb hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb lb lb figure 8 mode3 : 1-channel line-by-line analog input ( r , g , b ) cds 2 adck od [ 7 : 0 ] dly [ 1 : 0 ] = 00 hb : high byte ; lb : low byte hb lb hb lb 16 . 5 adck hb lb hb lb hb lb dly [ 1 : 0 ] = 01 dly [ 1 : 0 ] = 10 dly [ 1 : 0 ] = 11 hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb hb lb hb lb hb lb hb lb hb lb hb lb hb lb hb hb lb figure 9 mode4 : 1-channel line-by-line www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 13 november 24, 2011 HT82V46 reset level clamping (rlc) there are pixel-clamping and line-clamping two operating modes of HT82V46. it can be selected by register bit clpctl. the clamp switch controlled by an internal clp signal, and must set the rlcen (default=1) register bit to 1 to enable clamping. pixel-clamping (clpctl=0) ? when ws=0 (normal mode) and cds=x (both for cds mode and non-cds mode). the rlc switch is closed whenever the cds1 input pin is high, as shown in figure 10. ? when ws=1 and cds=1 (cds mode only) reset level clamping in ws mode is only possible in cds mode and the time at which the clamp switch is closed is concurrent with the reference sample period, c1 s , as shown in figure 11. rlc can be enabled on a pixel by pixel basis under control of the cds1 input pin. if cds1 is high when cds2 is high and is sampled by adck then clamping will be enabled for that input sample at the time determined by cdsref[1:0]. if cds1 is low at this point then the rlc switch will not be closed for that input sample. if rlc is required on every pixel then the cds1 pin can be constantly held high in ws mode. line-clamping (clpctl=1) ? ws=0 (normal mode) and cds=0 (non-cds mode) only. in situations where the input video signal does not have a stable reference level it may be necessary to clamp only during those pixels which have a known state (e.g. the dummy, or black pixels at the start or end of a line of most image sensors). this is known as line-clamping and relies on the input capacitor to hold the dc level between clamp intervals. in non-cds mode (cds=0) this can be done directly by controlling the cds1 input pin to go high during the black pixels only. alternatively it is possible to use cds1 to identify the black pixels and enable the clamp at the same time as the input is being sampled (i.e. when cds2 is high and cds1 is high). this mode is enabled by setting clpctl=1 and the operation is shown in figure 12. cds 1 cds 2 adck analog input clp figure 10 pixel-clamping rlc operation, with cds (non-cds also possible) cds 2 adck cdsref [ 1 : 0 ] = 00 cdsref [ 1 : 0 ] = 11 cdsref [ 1 : 0 ] = 10 cdsref [ 1 : 0 ] = 01 c 2 s c 2 s : video sample ; c 1 s : reference sample c 1 s c 1 s c 1 s c 1 s cds 1 cdsref [ 1 : 0 ] = 00 cdsref [ 1 : 0 ] = 11 cdsref [ 1 : 0 ] = 10 cdsref [ 1 : 0 ] = 01 clp clp clp clp rlc switch closed when cds 1 = 1 figure 11 ws mode (ws=1) rlc and sampling www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 14 november 24, 2011 HT82V46 cds 1 cds 2 adck analog input clp dummy or black pixel unstable ref . level video level figure 12 line-clamping rlc operation (non-cds only) summaries of the rlc switch control option rlc control register bit ws clpctl rlcen acyc lnbyln input is dc coupled and within supply range rlc is not enabled. rlc switch is always open. x x 0 x x input video signal has a suitable reference level rlc switch is controlled by cds1 pin. cds1=0/1 : switch is open/closed 0 0 1 x x pixel reference level not stable or need to clamp the black pixels of video period cds2 is normal, and cds1 is used to indicate black pixels location. rlc switch is controlled by cds1 and cds2 logical combination. cds1 & cds2=0/1: switch is open/closed 0 1 1 x x using ws mode cds1 pin as rlc/acyc pin, and the reference sample clock is gated by the ws internal timing generator, see figure 11. clp is an internal clamp switch control signal. clp=0/1 : clamp switch open/closed 1 x 1 x x using auto-cycling in ws mode cds1 pin as auto-cycling control and cant be clamp control signal. clpctl controls whether rlc is enabled or not. clpctl=0/1 : rlc is disabled/ enabled; see figure 11. 1 0 x 1 1 1 table 3 the options for the control of rlc switch www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 15 november 24, 2011 HT82V46 offset adjust and programmable gain the output from the cds block is a differential signal, which is added to the output of an 8-bit offset dac to compensate for offsets and then amplifed by a 8-bit pga. the gain and offset for each channel are independently programmable by writing to control bits dac[7:0] and pga[7:0]. in colour line-by-line mode the gain and offset coeffcients for each colour can be multiplexed in order (red green blue red) by pulsing the cds1 pin, or controlled via the acyc and intm[1:0] bits. refer to the line-by-line operation section for more details. adc input black level adjust the output from the pga can be offset to match the full-scale range of the differential adc (2 * (v rt - v rb )). negative-going input cideo signals the black level (zero differential) output from the pga should be offset to the top of the adc range by setting register bits pgafs[1:0]=10. this will give an output code of ffff (hex) from the HT82V46 for zero input. if code zero is required for zero differential input then the invod bit should be set. positive-going input video signals the black level should be offset to the bottom of the adc range by setting pgafs[1:0]=11. this will give an output code of 0000 (hex) from the HT82V46 for zero input. bipolar input video signals its accommodated by setting pgafs[1:0]=00 or pgafs[1:0]=01. zero differential input voltage gives mid-range adc output, 7fff (hex). signal flow summary see figure13 for overall signal fow diagram. input sampling block ? when cds=1 the previously sampled reference level v rl is subtracted from the input video v in . ? ? when cds=0 the simultaneously sampled voltage on pin vrlc/vbias is subtracted instead. ? ? if cdacpd=1 is an externally applied voltage on pin vrlc/vbias. ? if cdacpd=0 is the output from the internal rlc dac. v rlc = ( v cstep x cdac[3:0] ) + v cbot where : the step size of the rlc dac; : the minimum output of the rlc dac offset dac block the resultant signal v 1 is added to the offset dac output. v 2 = v 1 + (260mv x (dac[7:0] 127.5) ) / 127.5 pga block the signal is then multiplied by the pga gain. v 3 = v 2 + (0.66 + pga[8:0] x 7.34 / 511) adc block the analogue signal is then converted to a 16-bit unsigned number, with input range configured by pgafs[1:0]. ? pgafs[1:0]=0x d 1 [15:0]=int ( ( v 3 / v fs ) x 65535) + 32767 ? pgafs[1:0]=10 d 1 [15:0]=int ( ( v 3 / v fs ) x 65535) + 65535 ? pgafs[1:0]=11 d 1 [15:0]=int ( ( v 3 / v fs ) x 65535) + 0 where v fs : the adc full-scale range (lowref=0 / 1 then v fs = 2v / 1.2v) output invert block the polarity of the digital output may be inverted by control bit invod. ? invod=0 d 2 [15:0]= d 1 [15:0] ? invod=1 d 2 [15:0]= 65535 d 1 [15:0] output formats the output from the HT82V46 can be presented in several different formats under control of the odfm[1:0] register bits as shown in figure 14. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 16 november 24, 2011 HT82V46 8 9 + dac offset rlc dac 260 mv * ( dac [ 7 : 0 ] ?127 . 5 ) / 127 . 5 0 . 66 + pga [ 8 : 0 ] * 7 . 34 / 511 v in v 1 cds input sampling block + = 1 = 0 v rl v rlc cdacpd + - + v 2 + + offset dac block pga block x v 3 + adc block 4 2 pgafs [ 1 : 0 ] = 0 x : + 32768 = 10 : + 65535 = 11 : + 0 cdac [ 3 : 0 ] output invert block invod = 0 : d 2 = d 1 = 1 : d 2 = 65535 ? d 1 d 1 d 2 od [ 7 : 0 ] v in = vinr or ving or vinb v rl = v in sampled during ref . clamp v rlc = voltage applied to vrlc / vbias pin where * 65535 / v fs figure 13 overall signal flow hb : high byte ; lb : low byte hb lb hb lb ws = 0 hb lb hb lb hb lb hb lb hb hb hb hb hb hb hb lb hb lb hb lb ws = 1 hb nb 4 hb hb nb 3 nb 2 nb 1 nb 4 nb 3 nb 2 nb 1 nb 4 nb 3 nb 2 nb 4 ~ nb 1 : nibble ( nb 4 is the most significant ) odfm [ 1 : 0 ] = x 0 odfm [ 1 : 0 ] = 01 odfm [ 1 : 0 ] = x 0 odfm [ 1 : 0 ] = 01 odfm [ 1 : 0 ] = 11 t od t od od [ 7 : 0 ] adck od [ 7 : 0 ] od [ 7 : 0 ] od [ 7 : 0 ] od [ 7 : 4 ] figure 14 output data format www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 17 november 24, 2011 HT82V46 serial control interface the internal control registers are programmable and can be read-back via the serial control interface and pin od[7]/sdo. register write (a4=0) sck, sdi and sen are used for register writing. a address a[5:0] is clocked in through sdi, followed by a data word d[7:0]. each bit is latched on the rising edge of sck. when the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. register read-back (a4=1 and d[7:0] is dont cared at register write cycle) read-back is initiated by register write as described above but with a4 set to 1, followed by an 8-bit dummy data word. writing address (a5, 1, a3, a2, a1, a0) will cause the contents d[7:0] of corresponding register(a5, 1, a3, a2, a1, a0) to be output d[7:0] on pin sdo/od[7] at the falling edge of sck. sdo/od[7] is shared pin, therefore oeb pin should always be held low and the opd register bit should be set low when register read-back data is expected on this pin. the next word may be read in to sdi while the previous word is still being output on sdo/od[7] pin. note: to ensure all registers are set to their default values it is recommended that a software-reset is carried out after the power-up sequence, before writing to any other register. a 5 sck t sdis t sck t sdih a 4 a [ 3 : 0 ] d [ 7 : 0 ] sdi sen d 7 d 6 d [ 5 : 1 ] d 0 sdo / od [ 7 ] od [ 7 ] t ckfenr t enfckr t enfsd 7 t ckfsd 6 t ckfod 7 register write cycle oeb register write : a 4 = 0 register read - back : a 4 = 1 ( d [ 7 : 0 ] don t care at write cycle ) figure 15 serial control interface timing www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 18 november 24, 2011 HT82V46 control registers register mapping a[5:0] description por r/w d7 d6 d5 d4 d3 d2 d1 d0 01h setup register 1 03h rw ws mode4 pgafs[1:0] 2ch 1ch cds en 02h setup register 2 20h rw dly[1:0] cdacrng lowref opd invod odfm[1:0] 03h setup register 3 1fh rw ch[1:0] cdsref [1:0] cdac[3:0] 04h software reset 00h w D 05h auto-cycle reset 00h w D 06h setup register 4 00h rw 0 0 0 0 intm[1:0] acyc lnbyln 07h setup register 5 00h rw 0 cmlpd refpd cdacpd adcpd bpd gpd rpd 08h setup register 6 20h rw 0 clpctl rlcen c2pos c2dly[2:0] c2det 09h reserved 00h rw 0 0ah reserved 00h rw 0 0bh reserved 00h rw 0 0ch id 00h rw 0 id[3:0] 0dh reserved 00h rw 0 20h dac value (red) 80h rw dacr[7:0] 21h dac value (green) 80h rw dacg[7:0] 22h dac value (blue) 80h rw dacb[7:0] 23h dac value (rgb) 80h w dac[7:0] 24h pga gain (red) 00h rw 0 pgar[0] 25h pga gain (green) 00h rw 0 pgag[0] 26h pga gain (blue) 00h rw 0 pgab[0] 27h pga gain (rgb) 00h w 0 pga[0] 28h pga gain (red) 0dh rw pgar[8:1] 29h pga gain (green) 0dh rw pgag[8:1] 2ah pga gain (blue) 0dh rw pgab[8:1] 2bh pga gain (rgb) 00h w pga[8:1] www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 19 november 24, 2011 HT82V46 register description register bit no. name por. description setup register 1 0 en 1 global enable 0= complete power down 1= fully active 1 cds 1 sampling mode select 0= 2 or 3 channel 1= 1 channel. input channel selected by ch[1:0] bits and unused channels are powered down. 2 1ch 0 sampling mode select 0= 1 or 3 channel 1= 2 channel mode. input channels are red and green. blue channel is powered down. 3 2ch 0 sampling mode select 0= 1 or 3 channel 1= 2 channel mode. input channels are red and green. blue channel is powered down. 5:4 pgafs[1:0] 00 offsets pga output to optimize the adc range for different polarity sensor output signals. zero differential pga input signal gives: 0x= zero output from the pga, output=32767 10= full-scale positive output, output=65535; use for negative going video. set invod=1 if zero differential input should give a zero output code with negative going video. 11= full-scale negative output, output=0; use for positive going video 6 mode4 0 this bit has no effect when ws=0. set this bit when operating in ws mode 4. 0= other mode 1= ws mode 4 7 ws 0 makes the HT82V46 timing to the other operating mode selection 0= normal timing 1= enable ws timing. requires double rate adck and pixel rate cds2 input. cds1 pin performs same function as rlc/acyc pin. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 20 november 24, 2011 HT82V46 register bit no. name por. description setup register 2 1:0 odfm[1:0] 0 determines the output data format x0= 8 bits multiplexed (8+8 bits) 01= 8 bits parallel (8-msb only) 11= 4-bit multiplexed mode (4+4+4+4 bits). this mode is only valid when ws=1. 2 invod 0 digitally inverts the polarity of output data 3 opd 0 output disable. this works with the oeb pin to control the output pins. 0= digital outputs enabled 1= digital outputs high impedence oeb opd od 0 0 enabled 0 1 hi-z 1 0 hi-z 1 1 hi-z 4 lowref 0 reduces the adc reference range 2*(v rt C v rb ), thus changing the max/min input voltages. 0= adc reference range=2v 1= adc reference range=1.2v 5 cdacrng 1 sets the output range of the rlcdac 0= rlcdac ranges from 0 to avdd 1= rlcdac ranges from 0 to v rt 7:6 dly[1:0] 00 controls the latency from sample to data appearing on output pins ws = 0 = 1 = 1 timing modes all 1-2, 4-6 3 dly=00 7t 16.5t 23.5t dly=01 8t 18.5t 26.5t dly=10 9t 20.5t 29.5t dly=11 10t 22.5t 31.5t where t=adck periods setup register 3 3:0 cdac[3:0] 1111 controls rlcdac driving vrlc/vbias pin to defne ended signal reference voltage or reset level clamp voltage. D 5:4 cdsref[1:0] 01 when ws=0 these register bit have no effect. cds mode timing adjust. 00= advance reference sample by 1 adck period 01= default reference sample position 10= delay reference sample by 1 adck period 11= delay reference sample by 2 adck period D 7:6 ch[1:0] 00 when 1ch=0 these register bits have no effect. monochrome mode channel select. 00= select red channel 01= select green channel 10= select blue channel 11= reserved software D D D write this register will causes all function to be reset. it is recommended that a software reset be performed after a power on before any other register writes. auto-cycle reset D D D write this register will causes the auto-cycle counter to reset to vinr. this function is only required when lnbyln=1. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 21 november 24, 2011 HT82V46 register bit no. name por. description setup register 4 0 lnbyln 0 selects line by line operation. line by line operation is intended for use with systems which operate one line at a time but with up to three color shared on the one output. 1 acyc 0 if lnbyln=0 then acyc bit no effect. acyc bit determines cds1 pin and offset/gain register controls 0= cds1 pin is for reference sampling or reset level clamp control. and intm[1:0] bits are for gain/offset multiplexers control. 1= auto-cycling enabled by pulsing cds1 pin and input signal switched to next gain/offset register sequentially. and sequence is red -> green -> blue -> red etc. at this mode, it must set cds=0 and use clpctl bit instead cds1 pin to control rlc. 3:2 intm[1:0 00 when lnbyln=0 or acyc=1 this bit has no effect. when lnbyln=1 and acyc=0. controls the offset/gain mux selector. 00= red offset/gain registers applied to input channel. 01= green offset/gain registers applied to input channel. 10= blue offset/gain registers applied to input channel. 11= reserved. 7:4 reserved 0000 setup register 5 0 redpd 0 when set powers down red s/h, pga 1 grnpd 0 when set powers down green s/h, pga 2 blupd 0 when set powers down blue s/h, pga 3 adcpd 0 when set powers down adc, allows reduced power consumption without powering down the references which have a long time constant when switching on/off due to the external decoupling capacitors. 4 cdacpd 0 when set powers down 4-bit rlcdac, setting the output to a high impedance state and allowing an external reference to be driven in on the vrlc/vbias pin. 5 refpd 0 when set disables reft, refb buffers to allow external references to be used. 6 cmlpd 0 when set disable cml buffer to allow an externa reference to be used. 7 reserved 0 must be set to 0 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 22 november 24, 2011 HT82V46 register bit no. name por. description setup register 6 0 c2det 0 when ws=0 this register bit has no effect. when ws=1. 0= normal operation, signal on cds2 input pin is applied directly to timing control block. 1= programmable cds2 detect circuit is enabled. an internal synchronization pulse is generated from signal applied to cds2 input pin and is applied to timing control block on place of cds2. 3:1 c2dly[2:0] 000 when ws=0 or c2det=0 these bits have no effect. the c2dly bits set a programmable delay from the detected edge of the signal applied to the cds2 pin. the internally generated pulse is delayed by c2dly adck periods from the detected edge. 4 c2pos 0 when ws=0 or c2det=0 this bit has no effect when ws=1 and c2det=1 this bit controls whether positive or negative edges on the cds2 input pin are detected. 0= negative edge on cds2 pin is detected and used to generate internal timing pulse. 1= positive edge on cds2 pin is detected and used to generate internal timing pulse. 5 rlcen 1 reset level clamping enable. when set rlcen is enabled. the method of clamping is determined by clpctl and ws. in ws mode clamping will still occur on every pixel at a time defned by the cdsref[1:0] bits. 6 clpctl 0 this bit has no effect if ws=1. see table 3 for more information. 0= rlc switch is controlled directly from cds1 input pin. cds1= 0: switch is open cds1= 1: switch is close 1= rlc switch is controlled by logical combination of cds1 and cds2. cds1 & cds2=0 : switch is open. cds1 & cds2=1 : switch is close. 7 reserved 0 must be set to 0. id 7:4 reserved 0 must be set to 0. 3:0 id[3:0] 0000 id[3:0] these bits are storable and can be written from 0000 to 1111 values. but note that id[3:0] will be cleared to 0000 after power-on- reset. dac value (red) 7:0 dacr[7:0] 0 red channel 8-bit offset dac msb value. dac value (green) 7:0 dacg[7:0] 0 green channel 8-bit offset dac msb value. dac value (blue) 7:0 dacb[7:0] 0 blue channel 8-bit offset dac msb value. dac value (rgb) 7:0 dac[7:0] 0 write to this register will cause the r, g and b offset dac msb registers to be overwritten by the new value. pga gain (red) 0 pgar[0] 0 this register bit forms the lsb of the red channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 28 hex. pga gain (green) 0 pgag[0] 0 this register bit forms the lsb of the green channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 29 hex. pga gain (blue) 0 pgab[0] 0 this register bit forms the lsb of the blue channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 2a hex. pga gain (rgb) 0 pga[0] 0 writing a value to this location causes red, green and blue pga lsb gain values to be overwritten by the new value. pga gain (red) 7:0 pgar[8:1] 0d red pga gain setting register. 0.66+pgar[8:0]*7.34/511 pga gain (green) 7:0 pgag[8:1] 0d green pga gain setting register. 0.66+pgag[8:0]*7.34/511 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 23 november 24, 2011 HT82V46 register bit no. name por. description pga gain (blue) 7:0 pgab[8:1] 0d blue pga gain setting register. 0.66+pgab[8:0]*7.34/511 pga gain (rgb) 7:0 pga[8:1] 0 a write to this register will cause r, g and b pga gain registers to be overwritten by the new value. application circuits ht 82 v46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vinr ving vinb od [ 7 ]/ sdo od [ 6 ] od [ 5 ] od [ 4 ] od [ 3 ] od [ 2 ] od [ 1 ] od [ 0 ] sck sdi dvdd sen dvss adck cds 1 cds 2 oeb avss dvdd vrlc / vbias cml reft refb avss avdd video input 0 . 1 uf 0 . 01 uf 1 uf 0 . 1 uf 0 . 1 uf 0 . 1 uf timing control interface control avdd adc data output dvdd dvdd 0 . 1 uf 0 . 1 uf 0 . 1 uf dvdd 10 uf r e se r vo i r avdd 10 uf r e se r vo i r note: 1. all de-coupling capacitors should be ftted as close to HT82V46 as possible. 2. avss and dvss should be connected as close to HT82V46 as possible. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 24 november 24, 2011 HT82V46 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 28-pin ssop (209mil) outline dimensions ms-150 symbol dimensions in inch min. nom. max. a 0.291 D 0.323 b 0.197 D 0.220 c 0.009 D 0.013 c' 0.390 D 0.413 d D D 0.079 e D 0.026 D f 0.002 D D g 0.022 D 0.037 h 0.004 D 0.008 0 D 8 symbol dimensions in mm min. nom. max. a 7.40 D 8.20 b 5.00 D 5.60 c 0.22 D 0.33 c' 9.90 D 10.50 d D D 2.00 e D 0.65 D f 0.05 D D g 0.55 D 0.95 h 0.09 D 0.21 0 D 8 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 25 november 24, 2011 HT82V46 reel dimensions ssop 28s (209mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 28.4 +0.3/-0.2 t2 reel thickness 31.1 (max.) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 26 november 24, 2011 HT82V46 carrier tape dimensions

ssop 28s (209mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.2 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 8.40.1 b0 cavity width 10.650.10 k0 cavity depth 2.40.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 1.10 27 november 24, 2011 HT82V46 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-5631999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www. holtek.com.tw . www.datasheet.co.kr datasheet pdf - http://www..net/

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